1. Field of the Invention
The present invention relates to a data transmission system which transmits data, a transmission circuit and a reception circuit.
2. Description of the Related Art
Recently, the signal capacity of a communication IC (integrated circuit) has increased tremendously, and has reached a stage of transition from 40 Gbps to 100 Gbps in the practical area. Furthermore, 400 Gbps is going to be examined in the research area.
On the other hand, the processing clock frequency inside the IC has not kept up with this trend. That is, since it is not possible to perform processing using a high-speed clock inside the IC, processing of the signal is performed after an inputted high-speed signal is converted to a parallel signal to decrease the clock frequency.
Parallel conversion of a high-speed signal will be described below, with the case where the clock frequency inside an IC is 156 MHz in a SONET (Synchronous Optical NETwork)/SDH (Synchronous Digital Hierarchy) apparatus as an example.
In the case of a signal speed of 10 Gbps, it is necessary to convert the signal to a 64-bit width parallel signal inside the IC (10 Gbps/156 MHz=64 bits). In the case of a signal speed of 40 Gbps, it is necessary to convert the signal to a 256-bit width parallel signal inside the IC (40 Gbps/156 MHz=256 bits). Furthermore, in the case of a signal speed of 100 Gbps, it is necessary to convert the signal to a 640-bit width parallel signal inside the IC (100 Gbps/156 MHz=640 bits). Thus, as the signal speed is higher, the bit width of a parallel signal increases.
In the case where such a high-speed signal is latched by one stage by FFs (flip-flops) in the IC, 256 FFs are required for performing latching by only one stage if the signal speed is, for example, 40 Gbps. Therefore, the maximum number of synchronous output operations of the FFs is 256.
Furthermore, since a complicated logic is taken in the IC, more sets of FFs exist in the IC as the logic is deeper, and the number of synchronous operations further increases.
Therefore, as the communication capacity (communication speed) increases, switching noise due to the synchronous operations of the FFs inside the IC significantly increases. Consequently, there is a possibility that the switching noise cannot be suppressed no matter how many bypass capacitors for a power source line implemented outside the IC are added.
In the case of a CMOS-IC, power consumption inside the IC is proportional to the number of signal changes of the FFs. Therefore, as the number of synchronous operations increases, the power consumption of the IC increases.
Accordingly, there is widely known a method of reducing the number of synchronous operations by adding a 1-bit inversion instruction signal to a parallel signal (for example, see JP H02-310762A).
Referring to FIG. 1, there is disclosed a circuit disclosed in JP H02-310762A in which the number of synchronous operations for each clock is counted in comparison/judgment circuit 17, a polar signal is created in polar signal creation circuit 32 if the number of synchronous operations exceeds a criteria value, and the polarity of data is inverted with the use of the polar signal.
In recent fine processes, it is common to apply an ECC (Error Checking and Correction) circuit as a measure for memory soft errors (for example, see JP2006-179131A).
FPGA (Field Programmable Gate Array) manufacturers have a tendency to prepare a 72-bit width memory (RAM; Random Access Memory) as a standard, in consideration of applying this ECC circuit to an FPGA. This is because an 8-bit width ECC code correcting code is added to a 64-bit width main signal, so that the total bit width is 72 bits.